Advantages and disadvantages of MOSFET
Advantages and Disadvantages of MOSFET Scaling
Advantages of triple-well process
Analog Layout Design Tips and Tricks
Analog Layout Interview Questions
Antenna Effect in VLSI – Causes and Solution
Back End of the Line (BEOL) CMOS Fabrication Process Steps
Best Practice for Analog Layout Design
Characteristics of an ideal opamp
Characteristics of Operational Amplifier
CMOS process integration: FEOL & BEOL
Comparison Between SRAM and DRAM
Crosstalk Prevention techniques
DIBL(Drain Induced Barrier lowering)
Difference between Analog and digital layout?
Difference Between FinFET and MOSFET
Difference Between physical vapor deposition (PVD) and chemical vapor deposition (CVD)
Difference between statistical and conventional STA
Difference between the clock mesh and clock tree-type distribution system
Difference between the TTL chips and CMOS chips?
Different Types of IC Packaging
Digital Electronics Interview Question
Dishing and Erosion in Chemical Mechanical Planarization (CMP)
Double Patterning Technology Fabrication Process
During static timing analysis, what are the ideal characteristics of a clock?
Explain the concept of Asynchronous Reset.
Explain the working of 6-T SRAM cell
For timing analysis, what are the various paths that the designer considers?
Front End of the Line (FEOL) CMOS Fabrication Process Steps
High-speed layout how you will reduce resistance?
How do you calculate metal width and length?
How do you choose power metal?
How do you choose the height of Standard cells?
How do you plan for device placement?
How does FinFET reduce leakage?
How many types of clock jitter are there?
How many types of resets are available?
How many vias you will use and how it will help to reduce resistance?
How multiple vias are used to reduce crosstalk?
How STA is different from circuit simulation?
How STA is performed on the circuit?
How the spacing reduces the crosstalk?
How will you calculate negative and maximum borrow time?
How will you measure slack for setup and hold time?
How you will identify Analog and Digital layouts?
How you will take care of power in standard cells?
i/p’s and o/p’s of power planning and placement
Ideal MOSFET Current–Voltage Characteristics
Is the term clock skew and global skew the same?
List of Sanity Checks in Physical Design
List the ideal conditions for the timing path.
List the parameters on which net delay or cell delay depends.
List the types of delay models used to estimate the delay.
Memory Circuit and Layout Design Interview Question
MOS capacitance-voltage characteristics
Physical Design Interview Questions
Positive and Negative Clock Skew
Significance of CRPR in Static Timing Analysis
Speed Comparison Between SRAM and DRAM
TDDB(Time-Dependent Dielectric Breakdown)
Temperature Inversion on Lower Nodes
Types of Shielding in Analog Layout.
VLSI Interview Questions with Answers
What are reset assertion and reset Deassertion?
What are the constraints you will follow while doing standard cells?
What are the different types of delays in ASIC or VLSI design?
What are the effects of Metastability?
What are the important features of STA?
What are the main characteristics of the time-borrowing concept?
What are the main reasons for setup or hold time violations?
What are the major functions of STA?
What are the steps involved in semiconductor device fabrication?
What are the various timing paths?
What are the ways to reduce metal resistance?
What are the worst path and best paths?
What are Triple-Well Processes
What challenges did you face in lower node technologies?
What checks are done in Electrical rule check (ERC)
What do you mean by clock Jitter?
What do you mean by clock skew?
What do you mean by critical path, false path, and multicycle path?
What do you mean by Launch and capture edge?
What do you mean by positive, negative, and zero slack?
What do you mean by timing path? What are the start and endpoints?
What do you understand by time stealing?
What is a false path in static timing analysis?
What is a Programmable Logic Device
What is Channel Length Modulation
What is Double Patterning in VLSI
What is Double Patterning in VLSI
What is elf-aligned double-patterning (SADP)
What is meant by contact and via?
What is On-chip Variation (OCV)
What is Overshoot and Undershoot Glitch
What is pinch off effect in MOSFET
What is poly pitch?
What is positive, negative, and zero clock skew?
What is Schematic & Layout Design
What is synchronous reset along with its advantages and disadvantages?
What is the Contact Spike phenomenon in VLSI
What is the difference between higher and lower node technologies?
What is the difference between time-borrowing and time-stealing?
What is the importance of a good floorplan in analog layout design?
What is the odd cycle error in VLSI
What is the role of ERC in VLSI?
When Static Timing Analysis is done?
Where is FinFET technology used?
Which factors decide setup time and hold time?
Which input files are required to run STA?
Which net You will do shielding, clock net or signal net, and why?
Which type of jitters can be used to determine high-frequency jitter?
Why do we need Sense amplifiers and Precharge Circuit?
Why do we use p substrate in CMOS?
Why NAND Gate is Better than NOR Gate?
Why NMOS pass strong 0 and weak 1
Why PMOS pass strong 1 and weak 0
Why there is a pinch-off during the saturation mode of a CMOS device?
Why timing analysis is an important factor?
Why we are using Filler cells?
Working of ESD Clamp Circuit in VLSI
