STA Design Interview Questions
Difference between statistical and conventional STA
During static timing analysis, what are the ideal characteristics of a clock?
Explain the concept of Asynchronous Reset.
For timing analysis, what are the various paths that the designer considers?
How does FinFET reduce leakage?
How many types of clock jitter are there?
How many types of resets are available?
How STA is different from circuit simulation?
How STA is performed on the circuit?
How will you calculate negative and maximum borrow time?
How will you measure slack for setup and hold time?
Is the term clock skew and global skew the same?
List of Sanity Checks in Physical Design
List the ideal conditions for the timing path.
List the types of delay models used to estimate the delay.
What are reset assertion and reset Deassertion?
What are the different types of delays in ASIC or VLSI design?
What are the effects of Metastability?
What are the main characteristics of the time-borrowing concept?
What are the main reasons for setup or hold time violations?
What are the various timing paths?
What are the worst path and best paths?
What do you mean by clock Jitter?
What do you mean by clock skew?
What do you mean by critical path, false path, and multicycle path?
What do you mean by Launch and capture edge?
What do you mean by positive, negative, and zero slack?
What do you mean by timing path? What are the start and endpoints?
What do you understand by time stealing?
What is a false path in static timing analysis?
What is positive, negative, and zero clock skew?
What is synchronous reset along with its advantages and disadvantages?
What is the difference between time-borrowing and time-stealing?
When Static Timing Analysis is done?
Where is FinFET technology used?
Which factors decide setup time and hold time?
Which input files are required to run STA?
Which type of jitters can be used to determine high-frequency jitter?
